A Brief Study of Successive Cancellation Polar Decoder: Design and Performance Analysis

Abstract

Polar codes are emerging as a promising solution for error correction in modern communication systems, and Successive Cancellation Decoding (SCD) is the most widely used decoding algorithm for polar codes due to its simplicity and low computational complexity. This paper provides a brief study of the Successive Cancellation Polar Code Decoder, focusing on its design and performance analysis. We provide an overview of the SCD algorithm, its implementation, and its performance in terms of throughput and decoding latency. We designed and implemented the SC decoder on the Xilinx platform using Verilog HDL, achieving a latency of 3.351ns and throughput of 238.73 Mbps with on-chip dynamic power consumption of 4.14 watts and utilizing 446 LUTs. Our study shows that SCD can achieve high decoding throughput while maintaining low decoding latency and low power consumption, making it wellsuited for 5G wireless communication. This paper emphasizes the importance of careful design and correct implementation of processing elements for optimal performance in the SC decoder. The results of this study can contribute to the further development of efficient and reliable error-correcting codes for modern communication systems.